Altera

Description

Jan 30, 2015 XC6SLX16 . ISE 12.1 v1.08. ISE 13.1 Update v1.18(7). ISE 11.5 v1.06. ISE 13.2 v1.07. XC6SLX25. ISE 12.2 v1.11(6). ISE 13.1 Update v1.18(7). ISE 12.2 v1.11(6) . ISE 13.2 v1.07. XC6SLX25T. ISE 12.2 v1.11(6). ISE 13.1. Oct 25, 2011 Slices(2). Flip-Flops. Max. Distributed. RAM (Kb). 18 Kb(4). Max (Kb). XC6SLX4. 3,840. 600. 4,800. 75. 8. 12. 216. 2. 0. 0. 0. 4. 132. XC6SLX9. 9,152. 1,430. 11,440. 90. 16. 32. 576. 2. 2. 0. 0. 4. 200. XC6SLX16 . 14,579. 2,278. Jun 24, 2009 Spartan-6 FPGA Clocking Resources www.xilinx.com. UG382 (v1.9) December 20, 2013. DISCLAIMER. The information disclosed to you hereunder (the Materials ) is provided solely for the selection and use of Xilinx Jun 24, 2009 Spartan-6 FPGA Block RAM www.xilinx.com. UG383 (v1.5) July 8, 2011. Xilinx is disclosing this user guide, manual, release note, and/or specification (the Documentation) to you solely for use in the development of designs Where Low Cost, Low Power Converge with High Performance. When design requirements call for low cost and low power, the new Spartan -6 family is the answer. This silicon foundation of the Xilinx Targeted Design Platform merges