Altera

Description

The LMH0341 /0041/0071/0051 SDI Deserializers are. 23 5-Bit LVDS Interface part of TIs family of FPGA-Attach SER/DES products. No External VCO or Clock ABSTRACT. This application report discusses the LVDS timing requirements for the LMH0340 and LMH0341 family of products. Contents. 1. Introduction . Nov 28, 2007 Data Rate: 2.97 Gbps. X-Ref Target - Figure 2. Figure 2: LMH0341 Minimum Input Jitter Tolerance: 0.6UI. LMH0341 Sinusoidal Jitter Tolerance. Aug 20, 2008 Smart SerDes (LMH0340/ LMH0341 ) EVK - Contains ALP100 with Xilinx Spartan- 3E. FPGA, LMH0340 EVK (serializer), LMH0341 (deserializer);. Only one VCXO and passive loop filter required. LMH0340 and LMH0341 : SDI Serializer and Deserializer. 30 psP-P output alignment jitter (HD and 3G rates).