Altera

Description

Table 2 4 lists the Stratix III device EP3SL150F1152 pin count. U15. QDRII. Burst -of-four, 2M 18, 400-MHz QDRII memory interface in an FBGA package. J19. For example, the EP3SL150F1152 device supports four 18 groups on each The EP3SL150F1152 supports a total of eight PLLs, four DLLs, and 80 clock Page 1. 101 Innovation Drive San Jose, CA 95134 www.altera.com. Stratix III Development Kit. User Guide. Document Version: 1.1. Document Date:. Page 1. Stratix V Military Temperature Range Support. Technical Brief. 2015.12. 02. TB-110. Subscribe Send Feedback. As part of the Altera initiative to Page 1. Application Report. SLDA007A - August 2001 - Revised July 2003. 1 mini-LVDS Interface Specification. DSBU mini-LVDS. ABSTRACT. The trend