Altera

Description

DATASHEET Arria II GX EP2AGX260FF35 FPGA in the 1152-pin FineLine BGA (FBGA) package. . 244,188 LEs. . 102,600 adaptive logic modules (ALMs). . 11,756 Kbit Mar 1, 2010 EP2AGX95EF35 with EP2AGX190FF35 or EP2AGX260FF35 . EP2AGX125EF35 with EP2AGX190FF35 or EP2AGX260FF35 . Pins AJ8 and G8 Jul 1, 2010 EP2AGX95EF35 with EP2AGX190FF35 or EP2AGX260FF35 . EP2AGX125EF35 with EP2AGX190FF35 or EP2AGX260FF35 . Pins AJ8 and G8 Figure 2 2 shows the input reference clock sources for CMU PLLs and receiver CDRs in four transceiver blocks on the left side of the EP2AGX260FF35 device. Transceiver Block GXBL3. Channel 3. Channel 2. Channel 1. Channel 0. EP2AGX190FF35, EP2AGX260FF35 . CMU0. CMU1. CMU0. CMU1. CMU0. CMU1.